A Hardware-Efficient Algorithm for Real-Time Computation of Zadoff-Chu Sequences

A hardware-efficient algorithm and architecture for computing Zadoff–Chu (ZC) sequence elements on-line using the CORDIC algorithm are proposed. Zadoff–Chu sequences possess good correlation properties that are essential in a variety of engineering applications, such as establishing timing synchronization between a mobile terminal and a base station in the emerging 3GPP long-term evolution (LTE) physical layer standard for cellular communications. The proposed algorithm computes ZC-sequence elements both in time domain and frequency domain using a simple duality relationship. Algorithm transforms are employed to compute the elements recursively and eliminate the need for multipliers with non-constant terms. A reconfigurable hardware architecture was implemented and applied in a searcher block for detecting the physical random access channel (PRACH) in LTE. The PRACH provides a mechanism for a mobile to establish initial access along with uplink synchronization by transmitting a preamble that is constructed from ZC sequences. The proposed architecture is capable of generating these preambles on the fly with high accuracy, eliminating the need for storing a large number of long complex-valued ZC sequence elements. Simulation results demonstrate that the proposed architecture is capable of achieving detection error rates for LTE PRACH that are close to ideal rates achieved using floating point precision. (The work has been presented in part in Mansour (2009).) M. M. Mansour (B) American University of Beirut, Beirut, Lebanon e-mail: [email protected]